The present invention relates generally to a memory array architecture and more particularly to a high-speed array pipeline architecture used, for example, with a dynamic random access memory device (DRAM).
A typical DRAM memory device is comprised of a plurality of memory cells, each comprised of a transistor and a capacitor. The memory cells may be arranged in an array with each memory cell being connected to a wordline and a digitline. Each memory cell has a unique address. Each memory cell stores one bit of data in the form of a voltage. A high voltage level (e.g., Vcc) represents a logic “1”, whereas a low voltage level (e.g., 0V) represents a logic “0”. The DRAM may also include peripheral devices, such as logic circuits, drivers, decoders, sense amps, input/output devices, and power supplies, etc., that are used to identify memory cells, access the memory cells, store information within the memory cells, and read information from the memory cells, among others. Typically, the DRAM's control logic receives commands (e.g., read, write, etc.) and address information from a memory system controller. Row and column decoders decode the address information and the specific memory cell for which the command is directed is identified and the command executed.
FIG. 9 illustrates peripheral devices used by a DRAM according to the prior art. Two digitlines (e.g., D1, and D1*) and their associated peripheral devices are illustrated in FIG. 9. The digitlines (D1, D1*) are illustrated as being connected to two memory arrays (e.g., Array0 and Array1). The peripheral devices include equalization circuits (60a, 60b), isolation devices (such as transistors 61a, 61a*, 61b, and 61b*), input/output devices (such as transistors 63 and 63*), an n-sense amplifier 64, and a p-sense amplifier 62.
During a read operation, the digitlines D1 and D1* are initially equalized at a predetermined voltage (here Vcc/2) by setting ISOa*, ISOb*, EQa, and EQb high. One or more of these signals then transition low when an array is accessed. For example if Array0 is accessed, then EQa and ISOb* transition low (ISOb* is used to isolate Array1 digit capacitance from the sense amp to hasten the sensing operation).
Next, a selected wordline (not shown) is fired (i.e., activated) such that the memory cell (not shown) within Array0 identified by the address information from the memory controller is accessed (i.e., connected to its associated digitline). During the read operation, the memory cell shares its charge with its associated digitline. For example, assume that the identified cell is associated with digitline D1. When the memory cell's wordline is fired, the charge stored in the memory cell is shared with digitline D1. If the memory cell contains a stored logic one (e.g., Vcc), the charge sharing causes the voltage on digitline D1 to increase. If the memory cell contains a stored logic zero (e.g., GROUND), the charge sharing causes the voltage on digitline D1 to decrease. It should be noted that digitline D1* remains substantially at the precharge level Vcc/2 (the voltage of digitline D1* may change slightly due to parasitic coupling with, for example, D1 and the active wordline).
The differential voltage between the digitlines D1, D1* created when the memory cell is accessed is read or sensed by n-sense amplifier 64 and p-sense amplifier 62. Sensing generally refers to the amplification of the differential voltage between digitlines D1, D1* (i.e., the digitline signal). Because the differential voltage developed between digitlines D1 and D1* is used to read the memory cell contents, digitlines D1 and D1* are often referred to as a digitline pair. The sensed logic level is then output via input/output line I/O and its complement via is output via input/output line I/O* by activating the I/O transistors 63 and 63*, respectively, using a column select signal (CSEL).
During a write operation, the digitlines D1 and D1* are initially equalized at a predetermined voltage (here Vcc/2) by setting ISOa*, ISOb*, EQa, and EQb high. One or more of these signals then transition low when an array is accessed. For example if Array0 is accessed, then EQa and ISOb* transition low (ISOb* is used to isolate Array1 digit capacitance from the sense amp to hasten the sensing operation). A selected wordline (not shown) is fired such that the memory cell (not shown) within Array0 identified by the address information from the memory controller is accessed (i.e., connected to its associated digitline).
Next, a voltage logic level is then input via input/output lines I/O and I/O* by activating the I/O transistors 63 and 63* using CSEL. For example, a logic level 1 (i.e., Vcc) may be applied to digitline D1 via input/output line I/O and I/O transistor 63, whereas a logic level 0 (i.e., GROUND) may be applied to digitline D1* via input/output line I/O* and I/O transistor 63*. The new data states write over the existing data stored in the sense amplifiers (62, 64). After the sense amplifiers (62, 64) latch the new data, the I/O transistors (63, 63*) are shut down such that the sense amplifiers can restore the digitlines D1 and D1* (and thus, their associated, activated memory cells) to full levels. For example in the instant example, the memory cell associated with D1 is forced to logic 1, whereas the memory cell associated with D1* is forced to logic 0. The wordline is then deactivated when a precharge command is issued and the identified memory cell is disconnected from its associated wordline.
It should be apparent to one skilled in the art that above discussion has been simplified for clarity and that other operations or devices may be needed or used to effectively read data from, or write data to, a memory cell. For example, it should be apparent to one skilled in the art that the sense amplifiers (62, 64) may be bypassed and a logic level written directly to a selected memory cell.
FIG. 10 illustrates a simplified block diagram of a portion of a prior art memory system. The memory system includes a DRAM array 22 and peripheral circuits associated with digitline pair (D1-D1*). The peripheral circuits include equalization circuit 60, isolation transistors 61, p-sense amplifier 62, n-sense amplifier 64, input/output transistors 63, 63*, a column decode and driver circuit 71, a write driver 28, and a read sense-amplifier and driver 38. It should be apparent to one skilled in the art that the memory system illustrated in FIG. 10 is simplified and other components have been omitted as they are not required to form an understanding of the present invention.
As illustrated in FIG. 10, DRAM array 22 is accessed via digitlines D1 and D1* using a single column select line, a single input/output pair (I/O, I/O*), a single write driver 28, and a single read sense-amplifier and driver 38. This single column select architecture creates undesirable bottlenecks and increases the access time (i.e., the time it takes to read and/or write to a memory cell) required by the prior art memory system. These problems become more pronounced as processor speed and system clock frequency increase.
Thus, there exists a need for a high-speed array pipeline architecture that eliminates bottlenecks and which overcomes other limitations inherent in prior art.